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Application-specific integrated circuit

From Academic Kids

An ASIC (application-specific integrated circuit) is an integrated circuit (IC) customised for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. In contrast, a microprocessor is not, because users can adapt it to many purposes.

Using a purely commercial criterion, one could say that the intellectual property, design data base, application, distribution & sales are owned & controlled by an indiviual or company, and that individual company is almost always a separate entity to the device manufacturer. Often that individual or company is the end user or OEM (original equipment manufacturer) and the device is not available commercially.

Contrast this with the term Standard Product which is marketed & sold by the device manfacturer and so is freely available commercially.

Although the term ASIC can refer to both analogue and digital devices, the term is usually reserved for digital circuits.

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5000 gates to over 100 million. Modern ASICs often include entire 32-bit processors and other large building-blocks. Such an ASIC is often termed a SoC (System-on-a-chip). Designers of ASICs use a Hardware_description_language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.

For smaller designs and/or lower production volumes, ASICs have started to become a less attractive solution, as field-programmable gate arrays (FPGAs) grow larger, faster and more capable.

Contents

History

The initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customisation occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some base dies include RAM elements.

Standard Cell ASIC Design

In the 1980s, logic synthesis tools, such as Design Compiler, became available. Such tools could compile HDL descriptions into to a gate-level netlist. This enabled a style of design called standard-cell design. Standard-cell Integrated Circuits (ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice.

  1. A team of design engineers starts with a non-formal understanding of the required functions for a new ASIC, usually derived from Requirements analysis.
  2. The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is usually called the RTL (Register transfer level) design.
  3. Suitability for purpose is verified by simulation and/or Formal verification.
  4. A logic synthesis tool, such as Design Compiler, transforms the RTL design into a large collection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consists of pre-characterized collections of gates (such as 2 input nor, 2 input nand, invertors, etc.). The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist.
  5. The gate-level netlist is next processed by a placement tool which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints. Sometimes advanced techniques such as simulated annealing are used to optimise placement.
  6. The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a “sufficient” rather than “globally-optimal” solution. The output is a set of photomasks enabling a Semiconductor Fabrication to produce physical IC’s.
  7. Post Layout Simulations will be performed on extracted electrical data. This data is a netlist with the addition of estimates of the parasitic resistance and capacitance of the real circuit. In the case of a digital circuit, this will then be further mapped into delay information. Excessive delay, introduced by poor placement and routing can cause the circuit to function incorrectly. Only when satisfied that the device will function correctly over all extremes of the process, voltage and temperature will the design team allow the photomask information to be released for production.

These Design Steps (or flow) are also common to standard product design.

Semi-Custom ASIC Design

Semi-Custom design was a manufacturing method in which the diffused layers, i.e. the transistors & other active devices, were predefined and wafers containing such devices were held in stock prior to metalisation, in other words, unconnected. The physical design process would then define the interconnections of the final device. Non recurring engineering costs were much lower as photo lithographic masks are required only for the metal layers, and production cycles were much shorter as metalisation is a comparatively quick process.

The term "Semi-Custom" is almost synonymous and interchangeable with the term "Gate-Array". Which term you would use depends on who you are; if you were a process engineer, more likely than not you would use "Semi-Custom" whereas if you were a logic (or gate level) designer, "Gate-Array" would probably be your term of choice.

Semi-Custom ASICs were always a compromise as mapping a given design onto what a manufacturer held as a stock wafer would never give 100% utilization. Often difficulties in routing the interconnect required migration onto a larger array device with consequent increase in the piece part price.

Pure, logic only Semi-Custom Design is rarely offered as a service now, replaced almost entirely by Field Progammable Devices, such as FPGAs, which can be programmed locally and thus offer minimal tooling charges (Non Recurring Engineering(NRE)), marginally increased piece part cost and comparable performance. Sometimes reconfigurable Semi-Custom IP is offered, which would consist of a large IP core, like a processor, DSP unit etc & some reconfigurable uncommited logic, but again, this is quite rare.

Full-Custom ASIC Design

By contrast, Full-Custom ASIC Design defines all the photo lithographic layers of the device. Full Custom Design is used for both ASIC design & for Standard Product design.

The benefits of Full custom Design usually include reduced area, performance improvements and also the ability to integrate (include) analogue components and other pre-designed (& thus fully verified) components such as microprocesser cores etc that form a System-On-Chip.

The disadvantages of Full-Custom can include increased manufacturing time, increased non-recurring engineering costs, more complexity in the Computer Aided Design (CAD) system and a much higher skill requirement on the part of the design team.

However for digital only designs, "standard-cell" cell libraries together with modern CAD systems can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to "hand-tweak" or manually optimise any performance limiting aspect of the design.

Structured ASIC Design

Structure ASIC Design is an ambiguous expression, with different meanings in different contexts. Unfortunately it is often hi-jacked by advertising & marketing executives for product promotion, jumping on what might be called the "Structured Programming" bandwagon.

One definition states that "In a "structured ASIC" design, the logic mask-layers of a device are predefined and are usually supplied by a third party. Design differentiation and customization is achieved by creating custom metal layers that create custom connections between predifined lower-layer logic elements. "Structured ASIC" technology is seen as bridging the gap between field-programmable gate arrays and "standard-cell" ASIC designs. Because only a small number of chip layers must be custom-produced, "structured ASIC" designs have much smaller non-recurring expenditures (NRE) than "standard-cell" or "full-custom" chips, which require that a full mask set be produced for every design." which is effectively the same definition as a Gate Array.

Other definitions infer similarities to IP.

The best advice is to read carefully behind the advertising to achieve full understanding of that product offering.

Cell Libraries, IP-Based Design, Hard & Soft Macros

Cell Libraries of logical primitives are usually provided by the device manufacturer as part of the service. Although they will incurr no additional cost, their release will be covered by the terms of a non disclosure agreement (NDA) and they will be regarded as intellectual property by the manufacturer. Usually their physical design will be pre-defined as so they could be termed hard macros.

But what most engineers understand as Intellectual Property (IP) are designs purchased from a third party as sub-components of a larger ASIC. They may be provided as an HDL description (often termed a soft macro), or as a fully routed design that could be printed directly onto an ASIC’s mask (often termed a hard macro). Many organizations now sell such pre-designed IP, and larger organizations may have an entire department or division to produce such IP for the rest of the organization. For example, one can purchase CPUs, ethernet, USB or telephone interfaces. Indeed, the wide range of functions now available is a significant factor in the phenomenol increase in electronics in our lives; intellectual property takes a lot of time and investment to create, its re-use and further development cuts product cycle times dramatically and creates better products.

Soft Macros are often process independant i.e. they can be fabricated on a wide range of manufacturing prcesses & indeed different manufacturers.

Hard Macros are process limited and usually further design effort must be invested to migrate (port) to a different process or manufacturer.

Multi-Project Wafers

Some manufacturers offer MPW as a method of obtaing low cost prototypes. Often called shuttles, these MPW, containing several designs, run at regular, scheduled intervals on a "cut and go" basis, usually with very little liability on the part of the manufacturer. The contract involves the assembly & packaging of a handfull of devices. The service usually involves the supply of a physical design data base i.e. masking information or Pattern Generation (PG) tape. The manufacturer is often refered to as a "silicon foundry" due to the low involvement it has in the process.

External Links

  • ASIC Design Tutorial (http://www.tutorial-reports.com/hardware/asic/) A comprehensive description of the ASIC Design technology. Includes information on Design Description, Simulation, Synthesis, Verification and Extraction.
  • Designing ASICs (http://web.ukonline.co.uk/paul.naish/DA/contents.htm) An Introduction to ASIC design with an emphasis on synchronous clocking techniques. Written within the context of a training department. Perhaps rather dated now (1988) as it deals only with primitive logic. Analogue engineers who need to include some digital logic into their designs would find this particularly useful.
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